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Memory bus
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#	Item
251	HUNTing the Overlap Costin Iancu, Parry Husbands, Paul Hargrove Computational Research Division, Lawrence Berkeley National Laboratory {cciancu,pjrhusbands,phhargrove}@lbl.gov Abstract Add to Reading List Source URL: upc.lbl.gov Language: English - Date: 2010-05-06 00:14:40 Concurrency control Unified Parallel C InfiniBand Thread Universal Serial Bus Transmission Control Protocol Lock Remote direct memory access Computing Parallel computing Concurrent computing
252	7 System Interconnect[removed]a10_54004 Add to Reading List Source URL: www.altera.com Language: English - Date: 2013-12-02 03:56:37 Synchronous dynamic random-access memory DDR3 SDRAM Advanced Microcontroller Bus Architecture SDRAM Field-programmable gate array
253	Nios II 3C120 Microprocessor with LCD Controller Data Sheet DS[removed] © March 2009 Add to Reading List Source URL: www.altera.com Language: English - Date: 2009-04-22 16:48:22 Computer memory SDRAM Embedded systems IEEE standards Ethernet Media Independent Interface Dynamic random-access memory Nios II Serial Peripheral Interface Bus Computer hardware Computing Electronics
254	PSG2410 DATA SHEET Preliminary Low Dropout Regulator with On-Demand Power® for DDR Memory VDDQ Add to Reading List Source URL: www.packetdigital.com Language: English - Date: 2014-06-26 15:51:48 Linear regulator Voltage regulator Dropout voltage System Management Bus Low-dropout regulator Power supply Line regulation Load regulation Electrical engineering Electromagnetism Electronic engineering
255	External Memory Interfaces in Stratix V Devices Add to Reading List Source URL: www.altera.com Language: English - Date: 2014-07-02 07:29:55 Altera DQS Field-programmable gate array DDR2 SDRAM Synchronous dynamic random-access memory Dynamic random-access memory Bus Computer hardware Electronic engineering SDRAM
256	External Memory Interfaces in Stratix IV Devices Add to Reading List Source URL: www.altera.com Language: English - Date: 2010-06-29 02:55:29 Electronic engineering DDR SDRAM DQS Synchronous dynamic random-access memory Altera DDR2 SDRAM Bus Field-programmable gate array DDR3 SDRAM SDRAM Computer hardware Electronics
257	Modelling the Human and Technological Costs and Benefits of USB Memory Stick Security Adam Beautement UCL Robert Coles Add to Reading List Source URL: weis2008.econinfosec.org Language: English - Date: 2008-06-23 14:59:29 Crime prevention National security Public safety Data security USB flash drive Information security Universal Serial Bus Unemployment Countermeasure Security Computer security Computer network security
258	Architectural Considerations for CPU and Network Interface Integration C.D. Cranor, R. Gopalakrishnan, P. Z. Onufryk AT&T Labs - Research Florham Park, NJ Add to Reading List Source URL: chuck.cranor.org Language: English - Date: 2005-08-08 21:58:24 Computing Channel I/O Bus Cache Interrupt Cell Direct memory access Computer hardware Computer architecture Motherboard
259	CMPE 121 Project Report Ariel Anders Fall 2011 Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2013-10-03 13:49:43 Electronics Memory-mapped I/O Freescale 68HC11 Serial Peripheral Interface Bus EEPROM Universal asynchronous receiver/transmitter Booting Intel MCS-51 Atmel AVR Microcontrollers Computer hardware Computer architecture
260	Datasheet Vinculum-II Embedded Dual USB Host Controller IC Version 1.5 Document No.: FT_000138 Add to Reading List Source URL: www.ftdichip.com Language: English - Date: 2012-05-14 07:25:48 Quad-flat no-leads package USB flash drive Serial Peripheral Interface Bus Secure Digital Flash memory Embedded systems Embedded microprocessors Computer hardware Microcontrollers Universal Serial Bus

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